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? semiconductor components industries, llc, 2015 july, 2015 ? rev. 3 1 publication order number: kai?04070/d kai-04070 2048 (h) x 2048 (v) interline ccd image sensor description the kai?04070 image sensor is a 4-megapixel ccd in a 4/3 inch optical format. based on the truesense 7.4 micron interline transfer ccd platform, the sensor provides very high smear rejection and up to 82 db linear dynamic range through the use of a unique dual-gain amplifier. a flexible readout architecture enables use of 1, 2, or 4 outputs for full resolution readout up to 28 frames per second, while a vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. table 1. general specifications parameter typical value architecture interline ccd, progressive scan total number of pixels 2128 (h) 2112 (v) number of effective pixels 2080 (h) 2080 (v) number of active pixels 2048 (h) 2048 (v) pixel size 7.4 m (h) 7.4 m (v) active image size 15.2 mm (h) 15.2 mm (v), 21.4 mm (diagonal), 4/3 optical format aspect ratio 1:1 number of outputs 1, 2, or 4 charge capacity 44,000 electrons output sensitivity 8.7 v/e ? (low), 33 v/e ? (high) quantum efficiency pan (?aba, ?pba, ?qba) r, g, b (?cba) r, g, b (?fba) 52% 38%, 42%, 43% 37%, 42%, 41% read noise (f = 40 mhz) 12 e ? rms dark current photodiode vccd 3 e ? /s 145 e ? /s dark current doubling temp. photodiode vccd 7 c 9 c dynamic range high gain amp (40 mhz) dual amp, 2 2 bin (40 mhz) 70 db 82 db charge transfer efficiency 0.999999 blooming suppression > 1000 x smear ?115 db image lag < 10 electrons maximum pixel clock speed 40 mhz maximum frame rate quad output dual output single output 28 fps 14 fps 8 fps package 68 pin pga cover glass ar coated, 2 sides note: all parameters are specified at t = 40 c unless otherwise noted. features ? superior smear rejection ? up to 82 db linear dynamic range ? bayer color pattern, truesense sparse color filter pattern, and monochrome configurations ? progressive scan & flexible readout architecture ? high frame rate ? high sensitivity ? low noise architecture ? package pin reserved for device identification application ? industrial imaging and inspection ? traffic ? surveillance www.onsemi.com figure 1. kai?04070 interline ccd image sensor see detailed ordering and shipping information on page 2 o f this data sheet. ordering information
kai?04070 www.onsemi.com 2 the sensor is available with the truesense sparse color filter pattern, a technology which provides a 2x improvement in light sensitivity compared to a standard color bayer part. the sensor shares common pin-out and electrical configurations with a full family of truesense imaging interline transfer ccd image sensors, allowing a single camera design to be leveraged in support of multiple devices. ordering information table 2. ordering information ? kai?04070 image sensor part number description marking code kai?04070?aba?jd?ba monochrome, telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai?04070?aba serial number kai?04070?aba?jd?ae monochrome, telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai?04070?aba?jr?ba monochrome, telecentric microlens, pga package, taped clear cover glass with ar coating (both sides), standard grade kai?04070?aba?jr?ae monochrome, telecentric microlens, pga package, taped clear cover glass with ar coating (both sides), engineering grade 11kai?04070?fba?jd?ba gen2 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai?04070?fba serial number 11kai?04070?fba?jd?ae gen2 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade 11kai?04070?qba?jd?ba gen2 color (truesense sparse cfa), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai?04070?qba serial number 11kai?04070?qba?jd?ae gen2 color (truesense sparse cfa), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade 11kai?04070?cba?jd?ba* gen1 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai?04070?cba serial number 11kai?04070?cba?jd?ae* gen1 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade 11kai?04070?pba?jd?ba* gen1 color (truesense sparse cfa), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai?04070?pba serial number 11kai?04070?pba?jd?ae* gen1 color (truesense sparse cfa), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade *note recommended for new designs. table 3. ordering information ? evaluation support part number description g2?fpga?bd?14?40?a?gevk fpga board for it?ccd evaluation hardware kai?68pin?head?bd?a?gevb 68 pin imager board for it?ccd evaluation hardware lens?mount?kit?a?gevk lens mount kit for it?ccd evaluation hardware kai?68pin?n?probe?card?a?gevb 68 pin probe card (narrow socket) kai?68pin?w?probe?card?a?gevb 68 pin probe card (wide socket) see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com .
kai?04070 www.onsemi.com 3 device description architecture figure 2. block diagram 16 dark 16 v1b 16 buffer 16 16 24 ?????????????????? ?????????????????? h1s) 2048h x 2048v 7.4 m x 7.4 m pixels dark reference pixels there are 16 dark reference rows at the top and 16 dark rows at the bottom of the image sensor. the 24 dark columns on the left or right side of the image sensor should be used as a dark reference. under normal circumstances use only the center 22 columns of the 24 column dark reference due to potential light leakage. dummy pixels within each horizontal shift register there are 12 leading additional shift phases. these pixels are designated as dummy pixels and should not be used to determine a dark reference level. in addition, there is one dummy row of pixels at the top and bottom of the image. active buffer pixels 16 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. these pixels are light sensitive but are not tested for defects and non-uniformities. image acquisition an electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. these photoelectrons are collected locally by the formation of potential wells at each photosite. below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. when the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. esd protection adherence to the power-up and power-down sequence is critical. failure to follow the proper power-up and power-down sequences may cause damage to the sensor. see power-up and power-down sequence section.
kai?04070 www.onsemi.com 4 bayer color filter pattern figure 3. bayer color filter pattern 16 dark 16 v1b 16 buffer 16 16 24 ?????????????? ??????????????? 2048 (v) 7.4 m 7.4 m pixels (last vccd phase = v1 h1s) g b g r g b g r g b g r g b g r truesense sparse color filter pattern figure 4. truesense sparse color filter pattern 16 dark 16 v1b 16 buffer 16 16 24 ??????????????? ??????????????? ??????????????? 2048 (v) 7.4 m 7.4 m pixels (last vccd phase = v1 h1s) p g p g p r p r p b p b p g p g p g p g p r p r p b p b p g p g p g p g p r p r p b p b p g p g p g p g p r p r p b p b p g p g
kai?04070 www.onsemi.com 5 physical description pin description and device orientation figure 5. package pin designations ? top view v3b 68 esd 67 v3t 66 65 v4t v1t 64 63 v2t vddc 62 61 voutc gnd 60 59 rdcd rc 58 57 ogc h2slc 56 55 h2bc h1bc 54 53 h1sc h2sc 52 51 sub r2cd 50 49 h1sd h2sd 48 47 h2bd h1bd 46 45 ogd h2sld 44 43 rdcd rd 42 41 voutd gnd 40 39 v2t vddd 38 37 v4t v1t 36 35 devid v3t 1 v3b 3 4 v1b v4b 5 6 vdda v2b 7 8 gnd vouta 9 10 ra rdab 11 12 h2sla oga 13 14 h1ba h2ba 15 16 h2sa h1sa 17 18 r2ab sub 19 20 h2sb h1sb 21 22 h1bb h2bb 23 24 h2slb ogb 25 26 rb rdab 27 28 gnd voutb 29 30 vddb v2b 31 32 v1b v4b 33 34 esd pixel (1,1) table 4. package pin description pin name description 1 v3b vertical ccd clock, phase 3, bottom 3 v1b vertical ccd clock, phase 1, bottom 4 v4b vertical ccd clock, phase 4, bottom 5 vdda output amplifier supply, quadrant a 6 v2b vertical ccd clock, phase 2, bottom 7 gnd ground 8 vouta video output, quadrant a 9 ra reset gate, standard (high) gain, quadrant a 10 rdab reset drain, quadrants a & b 11 h2sla horizontal ccd clock, phase 2, storage, last phase, quadrant a 12 oga output gate, quadrant a 13 h1ba horizontal ccd clock, phase 1, barrier, quadrant a 14 h2ba horizontal ccd clock, phase 2, barrier, quadrant a 15 h2sa horizontal ccd clock, phase 2, storage, quadrant a 16 h1sa horizontal ccd clock, phase 1, storage, quadrant a 17 r2ab reset gate, low gain, quadrants a & b 18 sub substrate 19 h2sb horizontal ccd clock, phase 2, storage, quadrant b 20 h1sb horizontal ccd clock, phase 1, storage, quadrant b 21 h1bb horizontal ccd clock, phase 1, barrier, quadrant b
kai?04070 www.onsemi.com 6 table 4. package pin description (continued) pin description name 22 h2bb horizontal ccd clock, phase 2, barrier, quadrant b 23 h2slb horizontal ccd clock, phase 1, storage, last phase, quadrant b 24 ogb output gate, quadrant b 25 rb reset gate, standard (high) gain, quadrant b 26 rdab reset drain, quadrants a & b 27 gnd ground 28 voutb video output, quadrant b 29 vddb output amplifier supply, quadrant b 30 v2b vertical ccd clock, phase 2, bottom 31 v1b vertical ccd clock, phase 1, bottom 32 v4b vertical ccd clock, phase 4, bottom 33 v3b vertical ccd clock, phase 3, bottom 34 esd esd protection disable 35 v3t vertical ccd clock, phase 3, top 36 devid device identification 37 v1t vertical ccd clock, phase 1, top 38 v4t vertical ccd clock, phase 4, top 39 vddd output amplifier supply, quadrant d 40 v2t vertical ccd clock, phase 2, top 41 gnd ground 42 voutd video output, quadrant d 43 rd reset gate, standard (high) gain, quadrant d 44 rdcd reset drain, quadrants c & d 45 h2sld horizontal ccd clock, phase 2, storage, last phase, quadrant d 46 ogd output gate, quadrant d 47 h1bd horizontal ccd clock, phase 1, barrier, quadrant d 48 h2bd horizontal ccd clock, phase 2, barrier, quadrant d 49 h2sd horizontal ccd clock, phase 2, storage, quadrant d 50 h1sd horizontal ccd clock, phase 1, storage, quadrant d 51 r2cd reset gate, low gain, quadrants c & d 52 sub substrate 53 h2sc horizontal ccd clock, phase 2, storage, quadrant c 54 h1sc horizontal ccd clock, phase 1, storage, quadrant c 55 h1bc horizontal ccd clock, phase 1, barrier, quadrant c 56 h2bc horizontal ccd clock, phase 2, barrier, quadrant c 57 h2slc horizontal ccd clock, phase 2, storage, last phase, quadrant c 58 ogc output gate, quadrant c 59 rc reset gate, standard (high) gain, quadrant c 60 rdcd reset drain, quadrants c & d 61 gnd ground 62 voutc video output, quadrant c 63 vddc output amplifier supply, quadrant c 64 v2t vertical ccd clock, phase 2, top 65 v1t vertical ccd clock, phase 1, top 66 v4t vertical ccd clock, phase 4, top 67 v3t vertical ccd clock, phase 3, top 68 esd eds protection disable 1. liked named pins are internally connected and should have a common drive signal.
kai?04070 www.onsemi.com 7 imaging performance table 5. typical operational conditions (unless otherwise noted, the imaging performance specifications are measured using the following conditions. ) description condition notes light source continuous red, green and blue led illumination 1 operation nominal operating voltages and timing 1. for monochrome sensor, only green led used. specifications table 6. performance specifications description symbol min. nom. max. unit sampling plan temperature tested at ( c) all configurations dark field global non-uniformity dsnu ? ? 2.0 mvpp die 27, 40 bright field global non-uniformity (note 1) ? 2.0 5.0 % rms die 27, 40 bright field global peak to peak non-uniformity (note 1) prnu ? 5.0 15.0 % pp die 27, 40 bright field center non-uniformity (note 1) ? 1.0 2.0 % rms die 27, 40 maximum photoresponse non-linearity high gain (4,000 to 20,000 electrons) high gain (4,000 to 40,000 electrons) low gain (8,000 to 80,000 electrons) nl_hg1 nl_hg2 nl_lg1 ? ? ? 2 3 6 ? ? ? % design maximum gain difference between outputs (note 2) g ? ? 10 % design horizontal ccd charge capacity h ne ? 90 ? ke ? design vertical ccd charge capacity v ne ? 60 ? ke ? design photodiode charge capacity (note 3) p ne ? 44 ? ke ? die 27, 40 floating diffusion capacity ? high gain fne_hg 40 ? ? ke ? die 27, 40 floating diffusion capacity ? low gain fne_lg 160 ? ? ke ? die 27, 40 horizontal ccd charge transfer efficiency hcte 0.999995 0.999999 ? die vertical ccd charge transfer efficiency vcte 0.999995 0.999999 ? die photodiode dark current i pd ? 7 70 e/p/s die 40 vertical ccd dark current i vd ? 140 400 e/p/s die 40 image lag lag ? ? 10 e ? design anti-blooming factor x ab 1,000 ? ? design vertical smear smr ? ?115 ? db design read noise (note 4) high gain low gain n e?t ? 12 45 ? e ? rms design dynamic range, standard (notes 4, 5) dr ? 70.5 ? db design dynamic range, extended linear dynamic range mode (xldr) (notes 4, 5) xldr ? 82.5 ? db design output amplifier dc offset v odc ? 9.0 ? v die 27, 40 output amplifier bandwidth (note 6) f ?3db ? 250 ? mhz die output amplifier impedance r out ? 127 ? die 27, 40 output amplifier sensitivity high gain low gain v/ n ? ? 33 8.7 ? ? v/e ? design
kai?04070 www.onsemi.com 8 table 6. performance specifications (continued) description temperature tested at ( c) sampling plan unit max. nom. min. symbol kai?04070?aba and kai?04070?pba and kai?04070?qba configurations peak quantum efficiency qe max ? 52 ? % design peak quantum efficiency wavelength qe ? 500 ? nm design kai?04070?fba and kai?04070?qba gen2 color configurations peak quantum efficiency blue green red qe max ? ? ? 41 42 37 ? ? ? % design peak quantum efficiency wavelength blue green red qe ? ? ? 460 535 610 ? ? ? nm design kai?04070?cba and kai?04070?pba gen1 color configurations (note 7) peak quantum efficiency blue green red qe max ? ? ? 43 42 38 ? ? ? % design peak quantum efficiency wavelength blue green red qe ? ? ? 470 540 620 ? ? ? nm design 1. per color. 2. value is over the range of 10% to 90% of linear signal level saturation. 3. the operating value of the substrate voltage, v ab , will be marked on the shipping container for each device. the value of v ab is set such that the photodiode charge capacity is 440 mv. this value is determined while operating the device in the low gain mode. v ab value assigned is valid for both modes; high gain or low gain. 4. at 40 mhz. 5. uses 20log (p ne /n e?t ). 6. assumes 5 pf load. 7. this color filter set configuration (gen1) is not recommended for new designs. linear signal range figure 6. high gain linear signal range figure 7. low gain linear signal range output of sensor not verified 40,000 0 0 output signal (electrons) light or exposure (arbitrary) 20,000 30,000 10,000 1,320 output signal (mv) 990 660 330 0 4,000 132 nl_hg1 linearity range nl_hg2 linearity range high gain output of sensor not verified 160,000 0 0 output signal (electrons) 80,000 120,000 40,000 1,600 output signal (mv) 1,200 800 400 0 8,000 80 nl_lg1 linearity range low gain light or exposure (arbitrary)
kai?04070 www.onsemi.com 9 typical performance curves quantum efficiency monochrome with microlens figure 8. monochrome with microlens quantum efficiency color (bayer rgb) with microlens(gen2 and gen1 cfa) figure 9. color (bayer rgb) with microlens quantum efficiency
kai?04070 www.onsemi.com 10 color (truesense sparse cfa) with microlens (gen2 and gen1 cfa) figure 10. color (truesense sparse cfa) with microlens quantum efficiency angular quantum efficiency for the curves marked ?horizontal?, the incident light angle is varied in a plane parallel to the hccd. for the curves marked ?vertical?, the incident light angle is varied in a plane parallel to the vccd. monochrome with microlens figure 11. monochrome with microlens angular quantum efficiency angle (degrees) relative quantum efficiency (%) ?40 ?30 ?20 ?10 0 10 20 30 40 0 10 20 30 40 50 60 70 80 90 100 vertical horizontal
kai?04070 www.onsemi.com 11 color (bayer rgb) with microlens figure 12. color (bayer rgb) with microlens angular quantum efficiency angle (degrees) relative quantum efficiency (%) ?40 ?30 ?20 ?10 0 10 20 30 40 0 10 20 30 40 50 60 70 80 90 100 vertical horizontal dark current vs. temperature figure 13. dark current vs. temperature 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 dark current (e/s) 1000/t (k) photodiode vccd 0.01 0.10 1.00 10.00 100.00 1,000.00 10 c 20 c 30 c 40 c 50 c 60 c 70 c
kai?04070 www.onsemi.com 12 power-estimated power-estimated ? full resolution figure 14. power ? full resolution 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 5 10 15 20 25 30 35 40 power (w) power (w) hccd frequency (mhz) single dual (vouta/voutb) quad power-estimated ? 1/4 resolution ? 2 2 binning figure 15. power ? 1/4 resolution ? constant hccd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 5 10 15 20 25 30 35 40 power (w) power (w) hccd frequency (mhz) single dual (vouta/voutb) quad
kai?04070 www.onsemi.com 13 power-estimated ? 1/4 resolution ? 2 2 binning using variable hccd xldr figure 16. power ? 1/4 resolution ? variable hccd xldr 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 5 10 15 20 25 30 35 40 power (w) power (w) hccd frequency (mhz) single dual (vouta/voutb) quad power-estimated ? 1/4 resolution ? 2 2 binning using constant hccd xldr figure 17. power ? 1/4 resolution ? constant hccd xldr 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 5 10 15 20 25 30 35 40 power (w) power (w) hccd frequency (mhz) single dual (vouta/voutb) quad
kai?04070 www.onsemi.com 14 frame rates frame rates ? full resolution frame rates are for low and high gain modes of operation. figure 18. frame rates ? full resolution 0 5 10 15 20 25 30 35 40 hccd frequency (mhz) single dual (vouta/voutb) quad dual (vouta/voutc) 0 0 5 5 10 10 15 15 20 20 25 25 30 30 frame rate (fps) frame rate (fps) frame rates ? 1/4 resolution ? 2 2 binning frame rates are for low and high gain modes of operation. figure 19. frame rates ? 1/4 resolution ? constant hccd 0 5 10 15 20 25 30 35 40 hccd frequency (mhz) 0 0 5 5 10 10 15 15 40 40 45 45 50 50 single dual (vouta/voutb) quad dual (vouta/voutc) frame rate (fps) frame rate (fps) 20 20 25 25 30 30 35 35
kai?04070 www.onsemi.com 15 frame rates ? 1/4 resolution ? 2 2 binning using variable hccd xldr frame rates for variable hccd modes of operation. figure 20. frame rates ? 1/4 resolution ? variable hccd xldr 0 5 10 15 20 25 30 35 40 hccd frequency (mhz) 0 0 5 5 10 10 15 15 20 20 25 25 single dual (vouta/voutb) quad dual (vouta/voutc) 30 30 35 35 40 40 frame rate (fps) frame rate (fps) frame rates ? 1/4 resolution ? 2 2 binning using constant hccd xldr frame rates for a constant hccd mode of operation. figure 21. frame rates ? 1/4 resolution ? constant hccd xldr 0 5 10 15 20 25 30 35 40 hccd frequency (mhz) 0 0 5 5 10 10 15 15 20 20 25 25 single dual (vouta/voutb) quad dual (vouta/voutc) 30 30 35 35 40 40 frame rate (fps) frame rate (fps)
kai?04070 www.onsemi.com 16 defect definitions table 7. operation conditions for defect testing at 40 c description condition notes operational mode one output, using vouta, continuous readout hccd clock frequency 20 mhz pixels per line 2,140 lines per frame 2,112 line time 115.0 s frame time 242.9 ms photodiode integration time (pd_tint) pd_tint = frame time = 242.9 ms, no electronic shutter used temperature 40 c light source continuous red, green and blue led illumination 1 operation nominal operating voltages and timing 1. for monochrome sensor, only the green led is used. table 8. defect definitions for testing at 40 c description definition standard grade notes major dark field defective bright pixel defect 83 mv 40 1 major bright field defective pixel ?12% defect 12% 40 1 minor dark field defective bright pixel defect 41 mv 400 cluster defect a group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defect horizontally. 8 2 column defect a group of more than 10 contiguous major defective pixels along a single column. 0 2 1. for the color devices (kai?04070?cba and kai?04070?pba), a bright field defective pixel deviates by 12% with respect to pixel s of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ).
kai?04070 www.onsemi.com 17 table 9. operation conditions for defect testing at 27 c description condition notes operational mode one output, using vouta, continuous readout hccd clock frequency 20 mhz pixels per line 2,140 lines per frame 2,112 line time 115 s frame time 242.9 ms photodiode integration time (pd_tint) pd_tint = frame time = 242.9 ms, no electronic shutter used temperature 27 c light source continuous red, green and blue led illumination 1 operation nominal operating voltages and timing 1. for monochrome sensor, only the green led is used. table 10. defect definitions for testing at 40 c description definition standard grade notes major dark field defective bright pixel defect 27 mv 40 1 major bright field defective pixel ?12% defect 12% 40 1 cluster defect a group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defect horizontally. 8 2 column defect a group of more than 10 contiguous major defective pixels along a single column. 0 2 1. for the color devices (kai?04070?cba and kai?04070?pba), a bright field defective pixel deviates by 12% with respect to pixel s of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ). defect map the defect map supplied with each sensor is based upon testing at an ambient (27 c) temperature. minor point defects are not included in the defect map. all defective pixels are reference to pixel 1, 1 in the defect maps. see figure 22 for the location of pixel 1, 1.
kai?04070 www.onsemi.com 18 test definitions test regions of interest image area roi: pixel (1, 1) to pixel (2080, 2080) active area roi: pixel (17, 17) to pixel (2064, 2064) center roi: pixel (991, 991) to pixel (1090, 1090) only the active area roi pixels are used for performance and defect tests. overclocking the test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. see figure 22 for a pictorial representation of the regions of interest. figure 22. regions of interest vouta 1, 1 17, pixel pixel 16 dark rows 24 dark columns 16 buffer rows 16 buffer columns 16 buffer columns 24 dark columns 16 dark rows 16 buffer rows 17 2048 2048 active pixels tests dark field global non-uniformity this test is performed under dark field conditions. the sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. the average signal level of each of the 256 sub regions of interest is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: signal of roi[i] (roi average in counts units : mvpp (millivolts peak to peak) horizontal overclock average in counts) mv per count where i = 1 to 256. during this calculation on the 256 sub regions of interest, the maximum and minimum signal levels are found. the dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. global non-uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 924 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,320 mv. global non-uniformity is defined as global non?uniformity 100 active area standard deviation active area signal active area signal = active area average ? dark column average units : % rms
kai?04070 www.onsemi.com 19 global peak to peak non-uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 924 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,320 mv . the sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. the average signal level of each of the 256 sub regions of interest (roi) is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: signal of roi[i] (roi average in counts horizontal overclock average in counts) mv per count where i = 1 to 256. during this calculation on the 144 sub regions of interest, the maximum and minimum signal levels are found. the global peak to peak uniformity is then calculated as: global uniformity 100 max. signal min. signal active area signal units : % pp center non-uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 924 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,320 mv. defects are excluded for the calculation of this test. this test is performed on the center 100 by 100 pixels of the sensor. center uniformity is defined as: center roi uniformity 100 center roi standard deviation center roi signal center roi signal = center roi average ? dark colum average units : % rms dark field defect test this test is performed under dark field conditions. the sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. in each region of interest, the median value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the ?detect definitions? section. bright field defect test this test is performed with the imager illuminated to a level such that the output is at approximately 924 mv. prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,320 mv. the average signal level of all active pixels is found. the bright and dark thresholds are set as: dark defect threshold = active area signal threshold bright defect threshold = active area signal threshold the sensor is then partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. in each region of interest, the average value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. ? example for major bright field defective pixels: ? average value of all active pixels is found to be 924 mv ? dark defect threshold: 924 mv ? 12% = 111 mv ? bright defect threshold: 924 mv ? 12% = 111 mv ? region of interest #1 selected. this region of interest is pixels 17, 17 to pixels 144, 144 ? median of this region of interest is found to be 920 mv ? any pixel in this region of interest that is (920 ? 111 mv) 809 mv in intensity will be marked defective ? any pixel in this region of interest that is (920 + 111 mv) 1,031 mv in intensity will be marked defective ? all remaining 144 sub regions of interest are analyzed for defective pixels in the same manner
kai?04070 www.onsemi.com 20 operation absolute maximum ratings absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. if the level or the condition is exceeded, the device will be degraded and may be damaged. operation at these values will reduce mttf. table 11. absolute maximum ratings description symbol minimum maximum unit notes operating temperature t op ?50 70 c 1 humidity rh 5 90 % 2 output bias current i out ? 60 ma 3 off-chip load c l ? 10 pf stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. noise performance will degrade at higher temperatures. 2. t = 25 c. excessive humidity will degrade mttf. 3. total for all outputs. maximum current is ?15 ma for each output. avoid shorting output pins to ground or any low impedance source during operation. amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivi ty). table 12. absolute maximum voltage ratings between pins and ground description minimum maximum unit notes vdd , vout ?0.4 17.5 v 1 rd ?0.4 15.5 v 1 v1b, v1t esd ? 0.4 esd + 24.0 v v2b, v2t, v3b, v3t, v4b, v4t esd ? 0.4 esd + 14.0 v h1s , h1b , h2s , h2b , h2sl , r1 , r2 , og esd ? 0.4 esd + 14.0 v 1 esd ?10.0 0.0 v sub ?0.4 40.0 v 2 1. denotes a, b, c or d. 2. refer to application note using interline ccd image sensors in high intensity visible lighting conditions kai?08050 compatibility the kai?04070 is pin-for-pin compatible with a camera designed for the kai?08050 image sensor with the following accommodations: ? to operate in accordance with a system designed for kai?08050, the target substrate voltage should be set to be 2.0v higher than the value recorded on the kai?04070 shipping container. this setting will cause the charge capacity to be limited to 20 ke ? (or 660 mv) ? on the kai?04070, pins 17 (r2ab) and 51 (r2cd) should be left floating per the kai?08050 device performance specification ? the kai?04070 will operate in only the high gain mode (33 v/e ? ) ? all timing and voltages are taken from the kai?08050 specification sheet ? the number of horizontal and vertical ccd clock cycles is reduced as appropriate in addition, if the intent is to operate the kai?04070 image sensor in a camera designed for the kai?08050 sensor that has been modified to accept and process the full 40,000 e ? (1,320 mv) output, the following changes to the rd bias must be made: table 13. pins names kai?08050 kai?04070 10, 26, 44, 60 rda, rdb, rdc, rdd 12.0 v per the specification increase to 12.6 v to make use of the low or dual gains modes the kai?04070 voltages and timing specifications must be used.
kai?04070 www.onsemi.com 21 reset pin, low gain (r2ab and r2cd) the r2ab and r2bc (pins 17 and 51) each have an internal circuit to bias the pins to 4.3 v. this feature assures the device is set to operate in the high gain mode when pins 17 and 51 are not connected in the application to a clock driver (for kai?08050 compatibility). typical capacitor coupled drivers will not drive this structure. figure 23. equivalent circuit for reset gate, low gain (r2ab and r2cd) gnd vdd (+15 v) r2 4.3 v vdd (+15 v) 27 k 20 k 68 k gnd 27 k 20 k 68 k power-up and power-down sequence adherence to the power-up and power-down sequence is critical. failure to follow the proper power-up and power-down sequences may cause damage to the sensor. figure 24. power-up and power-down sequence vdd sub esd vccd low hccd low time v+ v? do not pulse the electronic shutter until esd is stable activate all other biases when esd is stable and sub is above 3 v 1. activate all other biases when esd is stable and sub is above 3 v. 2. do not pulse the electronic shutter until esd is stable. 3. vdd cannot be +15 v when sub is 0 v. 4. the image sensor can be protected from an accidental improper esd voltage by current limiting the sub current to less than 10 ma. sub and vdd must always be greater than gnd. esd must always be less than gnd. placing diodes between sub, vdd, esd and groun d will protect the sensor from accidental overshoots of sub, vdd and esd during power on and power off. see the figure below. notes:
kai?04070 www.onsemi.com 22 the vccd clock waveform must not have a negative overshoot more than 0.4 v below the esd voltage. figure 25. vccd clock waveform all vccd clock absolute maximum overshoot of 0.4 v 0.0 v esd esd ? 0.4 v example of external diode protection for sub, vdd and esd. denotes a, b, c or d. figure 26. example of external diode protection esd gnd vdd sub
kai?04070 www.onsemi.com 23 dc bias operating conditions table 14. dc bias operating conditions description pins symbol min. nom. max. unit max. dc current notes reset drain rd rd 12.4 12.6 12.8 v 10 a 1, 9 output gate og og ?2.2 ?2.0 ?1.8 v 10 a 1 output amplifier supply vdd v dd 14.5 15.0 15.5 v 11.0 ma 1, 2 ground gnd gnd 0.0 0.0 0.0 v ?1.0 ma substrate sub v sub 5.0 v ab v dd v 50 a 3, 8 esd protection disable esd esd ?9.2 ?9.0 vx_l v 50 a 6, 7, 10 output bias current vout i out ?3.0 ?5.0 ?10.0 ma ? 1, 4, 5 1. denotes a, b, c or d. 2. the maximum dc current is for one output. i dd = i out + i ss . see figure 27. 3. the operating value of the substrate voltage, v ab , will be marked on the shipping container for each device. the value of v ab is set such that the photodiode charge capacity is the nominal p ne (see specifications). 4. an output load sink must be applied to each vout pin to activate each output amplifier. 5. nominal value required for 40 mhz operation per output. may be reduced for slower data rates and lower noise. 6. adherence to the power-up and power-down sequence is critical. see sequence section. 7. esd maximum value must be less than or equal to v1_l + 0.4 v and v2_l + 0.4 v. 8. refer to application note using interline ccd image sensors in high intensity visible lighting conditions. 9. 12.0 v may be used if the total output signal desired is 20,000 e ? or less. 10. where vx_l is the level set for v1_l, v2_l, v3_l, or v4_l in the application. figure 27. output amplifier source follower #1 source follower #2 source follower #3 floating diffusion i ss i dd i out vout vdd r rd hccd og r2
kai?04070 www.onsemi.com 24 ac operating conditions table 15. clock levels description pins (note 1) symbol level min. nom. max. unit vertical ccd clock, phase 1 v1b, v1t v1_l low ?8.2 ?8.0 ?7.8 v v1_m mid ?0.2 0.0 0.2 v1_h high 11.5 12.0 12.5 vertical ccd clock, phase 2 v2b, v2t v2_l low ?8.2 ?8.0 ?7.8 v v2_h high ?0.2 0.0 0.2 vertical ccd clock, phase 3 v3b, v3t v3_l low ?8.2 ?8.0 ?7.8 v v3_h high ?0.2 0.0 0.2 vertical ccd clock, phase 4 v4b, v4t v4_l low ?8.2 ?8.0 ?7.8 v v4_h high ?0.2 0.0 0.2 horizontal ccd clock, phase 1 storage h1s h1s_l low ?5.2 ?4.0 ?3.8 v h1s_a amplitude (note 3) 3.8 4.0 5.2 horizontal ccd clock, phase 1 barrier h1b h1b_l low ?5.2 ?4.0 ?3.8 v h1b_a amplitude (note 3) 3.8 4.0 5.2 horizontal ccd clock, phase 2 storage h2s h2s_l low ?5.2 ?4.0 ?3.8 v h2s_a amplitude (note 3) 3.8 4.0 5.2 horizontal ccd clock, phase 2 barrier h2b h2b_l low ?5.2 ?4.0 ?3.8 v h2b_a amplitude (note 3) 3.8 4.0 5.2 horizontal ccd clock, last phase (note 2) h2sl h2sl_l low ?5.2 ?5.0 ?4.8 v h2sl_a amplitude (note 3) 4.8 5.0 5.2 reset gate r1 r_l low ?3.2 ?3.0 ?2.8 v r_a amplitude 6.0 ? 6.4 reset gate 2 r2 r2_l low ?2.0 ?1.8 ?1.6 v r2_a amplitude 6.0 ? 6.4 electronic shutter (note 4) sub ves high 29.0 30.0 40.0 v 1. denotes a, b, c or d. 2. use separate clock driver for improved speed performance. 3. the horizontal clock amplitude should be set such that the high level reaches 0.0 v. examples: a. if the minimum horizontal low voltage of ?5.2 v is used, then a 5.2 v amplitude clock is required for a clock swing of ?5.2 v t o 0.0 v. b. if the maximum horizontal low voltage of ?3.8 v is used, then a 3.8 v amplitude clock is required for a clock swing of ?3.8 v t o 0.0 v. 4. refer to application note using interline ccd image sensors in high intensity visible lighting conditions. the figure below shows the dc bias (vsub) and ac clock (ves) applied to the sub pin. both the dc bias and ac clock are referenced to ground. figure 28. dc bias and ac clock applied to the sub pin vsub ves gnd gnd
kai?04070 www.onsemi.com 25 capacitance table 16. capacitance v1b v2b v3b v4b v1t v2t v3t v4t gnd all pins unit v1b x 4 3 3 2 2 2 1 10 25 nf v2b x x 1 3 1 1 1 1 10 20 nf v3b x x x 5 2 1 2 1 6 23 nf v4b x x x x 2 1 1 1 13 23 nf v1t x x x x x 2 3 2 20 29 nf v2t x x x x x x 5 3 4 21 nf v3t x x x x x x x 2 9 24 nf v4t x x x x x x x x 3 20 nf vsub 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 2.8 2.8 nf h2s h1b h2b gnd all pins unit h1s 32 29 29 120 210 pf h2s x 16 21 170 240 pf h1b x x 7 155 210 pf h2b x x x 165 235 pf 1. tables show typical cross capacitance between pins of the device. 2. capacitance is total for all like pins. 3. capacitance values are estimated. device identification the device identification pin (devid) may be used to determine which truesense imaging 7.4 micron pixel interline ccd sensor is being used. table 17. device identification description pins symbol min. nom. max. unit max. dc current notes device identification devid devid 64,000 74,000 84,000 50 a 1, 2, 3 1. nominal value subject to verification and/or change during release of preliminary specifications. 2. if the device identification is not used, it may be left disconnected. 3. after device identification resistance has been read during camera initialization, it is recommended that the circuit be disa bled to prevent localized heating of the sensor due to current flow through the r_deviceid resistor. recommended circuit note that v1 must be a different value than v2. figure 29. device identification recommended circuit adc r_external v1 v2 devid gnd kai?04070 r_deviceid
kai?04070 www.onsemi.com 26 timing requirements and characteristics table 18. requirements and characteristics description symbol min. nom. max. unit notes photodiode transfer t pd 1.0 ? ? s vccd leading pedestal t 3p 4.0 ? ? s vccd trailing pedestal t 3d 4.0 ? ? s vccd transfer t v 2.0 ? ? s vccd clock cross-over v vcr 75 ? 100 % 1 vccd rise, fall times t vr , t vf 5 ? 10 % 1, 2 hccd delay t hs 2.0 ? ? s hccd transfer t e 25.0 ? ? ns shutter transfer t sub 2.0 ? ? s shutter delay t hd 2.0 ? ? s reset pulse t r 2.5 ? ? ns reset ? video delay t rv ? 2.2 ? ns h2sl ? video delay t hv ? 3.1 ? ns line time t line 34.9 ? ? s dual hccd readout 61.5 ? ? s single hccd readout frame time t frame 36.9 ? ? ms quad hccd readout 73.8 ? ? ms dual hccd readout 129.9 ? ? ms single hccd readout line time (xldr bin 2 2) t line 69.8 ? ? s dual hccd readout 123.0 ? ? s single hccd readout frame time (xldr bin 2 2) constant hccd timing t frame 36.9 ? ? ms quad hccd readout 73.7 ? ? ms dual hccd readout 129.9 ? ? ms single hccd readout frame time (xldr bin 2 2) variable hccd timing t frame 29.8 ? ? ms quad hccd readout 59.5 ? ? ms dual hccd readout 101.7 ? ? ms single hccd readout 1. refer to figure 47: vccd clock rise time, fall time, and edge alignment. 2. relative to the vccd transfer pulse width, t v .
kai?04070 www.onsemi.com 27 timing flow charts in the timing flow charts the number of hccd clock cycles per row, nh, and the number of vccd clock cycles per frame, nv, are shown in the following table. table 19. values for nh and nv when operating the sensor in the various modes of resolution full resolution 1/4 resolution xldr nv nh nv nh nv nh quad 1056 1076 528 538 528 538 dual vouta, voutc 1056 2152 528 1076 528 1076 dual vouta, voutb 2112 1076 1056 538 1056 538 single vouta 2112 2152 1056 1076 1056 1076 1. the time to read out one line t line = line timing + nh / (pixel frequency). 2. the time to read out one frame t frame = nv ? t line + frame timing. 3. line timing: see table 21: line timing. 4. frame timing: see table 20: frame timing. 5. xldr: extended linear dynamic range. no electronic shutter in this case the photodiode exposure time is equal to the time to read out an image. this flow chart applies to both full and 1/4 resolution modes. figure 30. timing flow when electronic shutter is not used frame timing (see table 20) line timing (see table 21) pixel timing (see table 22) repeat nh times repeat nv times
kai?04070 www.onsemi.com 28 using the electronic shutter this flow chart applies to both the full and 1/4 resolution modes. the exposure time begins on the falling edge of the electronic shutter pulse on the sub pin. the exposure time ends on the falling edge of the photodiode transfer (t pd ) of the v1t and v1b pins. the electronic shutter timing is shown in figure 38. figure 31. timing flow chart using the electronic shutter for exposure control frame timing (see table 20) line timing (see table 21) pixel timing (see table 22) repeat nh times repeat nv?nexp times electronic shutter timing line timing (see table 21) pixel timing (see table 22) repeat nh times repeat nexp times note: nexp: exposure time in increments of number of lines.
kai?04070 www.onsemi.com 29 timing tables frame timing this timing table is for transferring charge from the photodiodes to the vccd. see figures 32 and 33 for frame timing diagrams. table 20. frame timing device pin full resolution, high gain or low gain 1/4 resolution, high gain or low gain 1/4 resolution xldr quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta v1t f1t f1b f1t f1b f1t f1b v2t f2t f4b f2t f4b f2t f4b v3t f3t f3b f3t f3b f3t f3b v4t f4t f2b f4t f2b f4t f2b v1b f1b f1b f1b v2b f2b f2b f2b v3b f3b f3b f3b v4b f4b f4b f4b h1sa p1 p1q p1xl h1ba p1 p1q p1xl h2sa p2 p2q p2xl h2ba p2 p2q p2xl ra rhg/rlg rhgq/rlgq rxl h1sb p1 p1q p1xl h1bb p1 p2 p1 p2 p1q p2q p1q p2q p1xl p2xl p1xl p2xl h2sb p2 p2q p2xl h2bb p2 p1 p2 p1 p2q p1q p2q p1q p2xl p1xl p2xl p1xl rb rhg/ rlg (note 1) rhg/ rlg (note 1) rhgq/ rlgq (note 1) rhgq/ rlgq (note 1) rxl (note 1) rxl (note 1) r2ab r2hg/r2lg r2hgq/r2lgq r2xl h1sc p1 (note 1) p1q (note 1) p1xl (note 1) h1bc p1 (note 1) p1q (note 1) p1xl (note 1) h2sc p2 (note 1) p2q (note 1) p2xl (note 1) h2bc p2 (note 1) p2q (note 1) p2xl (note 1) rc rhg/rlg (note 1) rhgq/rlgq (note 1) rxl (note 1) h1sd p1 (note 1) p1q (note 1) p1xl (note 1) h1bd p1 p2 (note 1) p1q p2q (note 1) p1xl p2xl (note 1) h2sd p2 (note 1) p2q (note 1) p2xl (note 1) h2bd p2 p1 (note 1) p2q p1q (note 1) p2xl p1xl (note 1) rd rhg/ rlg (note 1) (note 1) rhgq/ rlgq (note 1) (note 1) rxl (note 1) (note 1) r2cd r2hg/r2lg (note 1) r2hgq/r2lgq (note 1) r2xl (note 1) shp (note 2) shp1 shpq (note 4) shd (note 2) shd1 shdq (note 5) 1. this clock should be held at its high level voltage (0 v) or held at +5.0 v for compatibility with truesense 5.5 micron interli ne transfer ccd family of products. 2. shp and shd are the sample clocks for the analog front end (afe) signal processor. 3. this note intentionally left empty. 4. use shplg for the afe processing the low gain signal. use shphg for the afe processing the high gain signal. 5. use shdlg for the afe processing the low gain signal. use shdhg for the afe processing the high gain signal.
kai?04070 www.onsemi.com 30 line timing this timing is for transferring one line of charge from the vccd to the hccd. see figure 34, figure 35, figure 36 and figure 37 for line timing diagrams. table 21. line timing device pin full resolution, high gain or low gain 1/4 resolution, high gain or low gain 1/4 resolution xldr quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta v1t l1t l1b 2 l1t 2 l1b 2 l1t 2 l1b v2t l2t l4b 2 l2t 2 l4b 2 l2t 2 l4b v3t l3t l3b 2 l3t 2 l3b 2 l3t 2 l3b v4t l4t l2b 2 l4t 2 l2b 2 l4t 2 l2b v1b l1b 2 l1b 2 l1b v2b l2b 2 l2b 2 l2b v3b l3b 2 l3b 2 l3b v4b l4b 2 l4b 2 l4b h1sa p1l p1lq p1xl h1ba p1l p1lq p1xl h2sa p2l p2lq p2xl h2ba p2l p2lq p2xl ra rhg/rlg rhgq/rlgq rxl h1sb p1l p1lq p1xl h1bb p1l p2l p1l p2l p1lq p2lq p1lq p2lq p1xl p2xl p1xl p2xl h2sb p2l p2lq p2xl h2bb p2l p1l p2l p1l p2lq p1lq p2lq p1lq p2xl p1xl p2xl p1xl rb rhg/ rlg (note 1) rhg/ rlg (note 1) rhgq/ rlgq (note 1) rhgq/ rlgq (note 1) rxl (note 1) rxl (note 1) r2ab r2hg/r2lg r2hgq/r2lgq r2xl h1sc p1l (note 1) p1lq (note 1) p1xl (note 1) h1bc p1l (note 1) p1lq (note 1) p1xl (note 1) h2sc p2l (note 1) p2lq (note 1) p2xl (note 1) h2bc p2l (note 1) p2lq (note 1) p2xl (note 1) rc rhg/rlg (note 1) rhgq/rlgq (note 1) rxl (note 1) h1sd p1l (note 1) p1lq (note 1) p1xl (note 1) h1bd p1l p2l (note 1) p1lq p2lq (note 1) p1xl p2xl (note 1) h2sd p2l (note 1) p2lq (note 1) p2xl (note 1) h2bd p2l p1l (note 1) p2lq p1lq (note 1) p2xl p1xl (note 1) rd rhg/ rlg (note 1) (note 1) rhgq/ rlgq (note 1) (note 1) rxl (note 1) (note 1) r2cd r2hg/r2lg (note 1) r2hgq/r2lgq (note 1) r2xl (note 1) shp (note 2) shp1 shpq (note 4) shd (note 2) shd1 shdq (note 5) 1. this clock should be held at its high level voltage (0 v) or held at +5.0 v for compatibility with truesense 5.5 micron interli ne transfer ccd family of products. 2. shp and shd are the sample clocks for the analog front end (afe) signal processor. 3. the notation 2 l1b means repeat the l1b timing twice for every line. this sums two rows into the hccd. 4. use shplg for the afe processing the low gain signal. use shphg for the afe processing the high gain signal. 5. use shdlg for the afe processing the low gain signal. use shdhg for the afe processing the high gain signal.
kai?04070 www.onsemi.com 31 pixel timing this timing is for transferring one pixel from the hccd to the output amplifier. table 22. pixel timing device pin full resolution, high gain or low gain 1/4 resolution, high gain or low gain 1/4 resolution xldr quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta v1t ?8 v ?8 v ?8 v v2t ?8 v ?8 v ?8 v v3t 0v 0v 0v v4t 0v 0v 0v v1b ?8 v ?8 v ?8 v v2b 0v 0v 0v v3b 0v 0v 0v v4b ?8 v ?8 v ?8 v h1sa p1 p1q p1xl h1ba p1 p1q p1xl h2sa p2 p2q p2xl h2ba p2 p2q p2xl ra rhg/rlg rhgq/rlgq rxl h1sb p1 p1q p1xl h1bb p1 p2 p1 p2 p1q p2q p1q p2q p1xl p2xl p1xl p2xl h2sb p2 p2q p2xl h2bb p2 p1 p2 p1 p2q p1q p2q p1q p2xl p1xl p2xl p1xl rb rhg/ rlg (note 1) rhg/ rlg (note 1) rhgq/ rlgq (note 1) rhgq/ rlgq (note 1) rxl (note 1) rxl (note 1) r2ab r2hg/r2lg r2hgq/r2lgq r2xl h1sc p1 (note 1) p1q (note 1) p1xl (note 1) h1bc p1 (note 1) p1q (note 1) p1xl (note 1) h2sc p2 (note 1) p2q (note 1) p2xl (note 1) h2bc p2 (note 1) p2q (note 1) p2xl (note 1) rc rhg/rlg (note 1) rhgq/rlgq (note 1) rxl (note 1) h1sd p1 (note 1) p1q (note 1) p1xl (note 1) h1bd p1 p2 (note 1) p1q p2q (note 1) p1xl p2xl (note 1) h2sd p2 (note 1) p2q (note 1) p2xl (note 1) h2bd p2 p1 (note 1) p2q p1q (note 1) p2xl p1xl (note 1) rd rhg/ rlg (note 1) (note 1) rhgq/ rlgq (note 1) (note 1) rxl (note 1) (note 1) r2cd r2hg/r2lg (note 1) r2hgq/r2lgq (note 1) r2xl (note 1) shp (note 2) shp1 shpq (note 4) shd (note 2) shd1 shdq (note 5) 1. this clock should be held at its high level voltage (0 v) or held at +5.0 v for compatibility with truesense 5.5 micron interli ne transfer ccd family of products. 2. shp and shd are the sample clocks for the analog front end (afe) signal processor. 3. this note intentionally left empty. 4. use shplg for the afe processing the low gain signal. use shphg for the afe processing the high gain signal. 5. use shdlg for the afe processing the low gain signal. use shdhg for the afe processing the high gain signal.
kai?04070 www.onsemi.com 32 timing diagrams the charge in the photodiodes its transfer to the vccd on the rising edge of the +12 v pulse and is completed by the falling edge of the +12 v pulsed on f1t and f1b. during the time period when f1t and f1b are at +12 v (t pd ) anti-blooming protection is disabled. the photodiode integration time ends on the falling edge of the +12 v pulse. frame timi ng ? quadrant and d ual vouta/v outc readout modes figure 32. frame timing diagram quadrant and dual vouta/voutc readout modes f1t f2t f3t f4t f1b f2b f3b f4b +12 v 0 v ?8 v +12 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v v1b v2b v3b v4b v1t v2t v3t v4t frame timing device pin pattern t 3p t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t 3d t pd frame timing line timing pixel timing t 3p t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t 3d t pd note: see table 20 for pin assignments.
kai?04070 www.onsemi.com 33 frame t iming ? single and dual v outa/voutb readout modes figure 33. frame timing diagram single and dual vouta/voutb readout modes f1b f4b f3b f2b f1b f2b f3b f4b +12 v 0 v ?8 v +12 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v v1b v2b v3b v4b v1t v2t v3t v4t frame timing device pin pattern t 3p t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t 3d t pd frame timing line timing pixel timing t 3p t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t 3d t pd note: see table 20 for pin assignments.
kai?04070 www.onsemi.com 34 line t iming ?full resolution ? quadrant and dual vouta/voutc readout modes figure 34. line timing diagram ? full resolution ? quadrant and dual vouta/voutc readout modes device pin pattern frame or pixel timing line timing pixel timing t v 2 note: see table 21 for pin assignments. l1t l2t l3t l4t l1b l2b l3b l4b 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v p1l 0 v ?4 v 0 v ?4 v p2l v1b v2b v3b v4b v1t v2t v3t v4t hor izont al cl ocks t e 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 time duration is 4 ? t v line timing t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2
kai?04070 www.onsemi.com 35 line t iming ?full resolution ? single and dual vouta/voutb readout modes figure 35. line timing diagram ? full resolution ? single and dual vouta/voutb readout modes device pin pattern frame or pixel timing line timing pixel timing t v 2 note: see table 21 for pin assignments. l1b l4b l3b l2b l1b l2b l3b l4b 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v p1l 0 v ?4 v 0 v ?4 v p2l v1b v2b v3b v4b v1t v2t v3t v4t hor izont al cl ocks t e 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 time duration is 4 ? t v line timing t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2
kai?04070 www.onsemi.com 36 line timing ? low gain, high gain and xldr 1/4 resolution ? quadrant and dual vouta/v outc readout modes figure 36. line timing diagram ? 1/4 resolution ? quadrant and dual vouta/voutc readout modes device pin pattern frame or pixel timing 1/4 resolution line timing pixel timing t v 2 note: see table 21 for pin assignments. t e 2 time duration is 8 ? t v l1t l2t l3t l4t l1b l2b l3b l4b p1l p2l 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?4 v 0 v ?4 v v1b v2b v3b v4b v1t v2t v3t v4t hor izont al cl ocks t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 1/4 resolution line timing t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2
kai?04070 www.onsemi.com 37 line timing ? low gain, high gain and xldr 1/4 resolution ? single and dual vouta/v outb readout modes figure 37. line timing diagram ? 1/4 resolution ? single and dual vouta/voutb readout modes device pin pattern frame or pixel timing 1/4 resolution line timing pixel timing t v 2 note: see table 21 for pin assignments. t e 2 time duration is 8 ? t v l1b l4b l3b l2b l1b l2b l3b l4b p1l p2l 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?8 v 0 v ?4 v 0 v ?4 v v1b v2b v3b v4b v1t v2t v3t v4t hor izont al cl ocks t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 1/4 resolution line timing t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2 t v 2
kai?04070 www.onsemi.com 38 electronic shutter timing diagrams the electronic shutter pulse can be inserted at the end of any line of the hccd timing. the hccd should be empty when the electronic shutter is pulsed. a recommended position for the electronic shutter is just after the last pixel is read out of a line. the vccd clocks should not resume until at least t v /2 after the electronic shutter pulse has finished. the hccd clocks can be run during the electronic shutter pulse as long as the hccd does not contain valid image data. for short exposures less than one line time, the electronic shutter pulse can appear inside the frame timing. any electronic shutter pulse transition should be t v /2 away from any vccd clock transition. figure 38. electronic shutter timing t v 2 sub vab ves 0 v ?8 v vccd clock t sub t v 2 figure 39. frame/electrical shutter timing t int v1t/v1b sub t frame
kai?04070 www.onsemi.com 39 pixel t iming ? full resolution ? high gain pixel timing use this timing to read out every pixel at high gain. if the sensor is to be permanently operated at high gain, the r2ab and r2cd pins can be left floating or set to any dc voltage between +3 v and +5 v. note the r2ab and r2cd pins are internally biased to +4.3 v when left floating. the shp1 and shd1 pulses indicate where the camera electronics should sample the video waveform. the shp1 and shd1 pulses are not applied to the image sensor. figure 40. pixel timing diagram ? full resolution ? high gain 0 v ?4 v 0 v ?4 v +4.2 v ?1.8 v +3 v ?3 v device pin pattern hor izont al cl ocks video vout rhg r r2hg r2 shp1 shd1 p1 p2 t e t r
kai?04070 www.onsemi.com 40 pixel t iming ? full resolution ? low gain pixel timing use this pixel timing to read out every pixel at low gain. if the sensor is to be permanently operated at low gain, the ra, rb, rc and rd pins should be set to any dc voltage between +3 v and +5 v. the shp1 and shd1 pulses indicate where the camera electronics should sample the video waveform. the shp1 and shd1 pulses are not applied to the image sensor. figure 41. pixel timing diagram ? full resolution ? low gain 0 v ?4 v 0 v ?4 v +4.2 v ?1.8 v +3 v ?3 v device pin pattern hor izont al cl ocks video vout rlg r r2lg r2 shp1 shd1 p1 p2 t e t r
kai?04070 www.onsemi.com 41 pixel t iming ? 1/4 resolution ? high gain pixel timing use this timing to read out two pixels summed on the output amplifier sense node at high gain. if the sensor is to be permanently operated at high gain, the r2ab and r2cd pins can be left floating or set to any dc voltage between +3 v and +5 v. note the r2ab and r2cd pins are internally biased to +4.3 v when left floating. the shpq and shdq pulses indicate where the camera electronics should sample the video waveform. the shpq and shdq pulses are not applied to the image sensor. the ra, rb, rc, and rd pins are pulsed at half the frequency of the horizontal ccd clocks. this causes two pixels to be summed on the output amplifier sense node. the shpq and shdq clocks are also half the frequency of the horizontal ccd clocks. device pin pattern hor izont al cl ocks video vout rhgq r r2hgq r2 shp1 shd1 p1q p2q t e figure 42. pixel timing diagram ? 1/4 resolution ? high gain 0 v ?4 v 0 v ?4 v +4.2 v ?1.8 v +3 v ?3 v 2 ? t e t r
kai?04070 www.onsemi.com 42 pixel t iming ? 1/4 resolution ? low gain pixel timing use this timing to read out two pixels summed on the output amplifier sense node at low gain. if the sensor is to be permanently operated at low gain, the ra, rb, rc and rd pins can be set to any dc voltage between +3 v and +5 v. the shpq and shdq pulses indicate where the camera electronics should sample the video waveform. the shpq and shdq pulses are not applied to the image sensor. the r2ab and r2cd pins are pulsed at half the frequency of the horizontal ccd clocks. this causes two pixels to be summed on the output amplifier sense node. the shpq and shdq clocks are also half the frequency of the horizontal ccd clocks. device pin pattern hor izont al cl ocks video vout rlgq r r2lgq r2 shp1 shd1 p1q p2q t e figure 43. pixel timing diagram ? 1/4 resolution ? low gain 0 v ?4 v 0 v ?4 v +4.2 v ?1.8 v +3 v ?3 v 2 ? t e t r
kai?04070 www.onsemi.com 43 xldr pixel timing to operate the sensor in extended linear dynamic range (xldr) mode, the following pixel timing should be used. this mode requires two sets of analog front end (afe) signal processing electronic units for each output. as shown in figure 44 one afe samples the pixel at low gain (shplg and shdlg) and the other afe samples the pixel at high gain (shphg and shdhg). two hccd pixels are summed on the output amplifier node to obtain enough charge to fully use the 82 db range of the xldr timing. combined with two-line vccd summing, a total of 160,000 electrons of signal (4 40,000) can be sampled with 12 electrons or less noise. note that a linear dynamic range of 82 db is very lar ge. ensure that the camera optics is capable of focusing an 82 db dynamic range image on the sensor. lens flare caused by inexpensive optics or even dust on the lens will limit the dynamic range. the timing shown in figure 46 shows the hccd not being clocked at a constant frequency. if the hccd cannot be clocked at a variable frequency, then the hccd may be clocked at a constant frequency (figure 45) at the expense of about 33% slower frame rate. figure 44. xldr timing ? afe connections block diagram low gain afe high gain afe shpl g shdl g shphg shdhg sensor output low gain digital out high gain digital out caution: in the xldr mode the output of the ccd can produce large signals that may damage some afe devices. if there is the potential for damage to the afe, the ccd output should be electronically attenuated.
kai?04070 www.onsemi.com 44 pixel t iming ? 1/4 resolution ? xldr pixel timing ? constant hccd t iming device pin pattern hor izont al cl ocks video vout rxl r p2xl t e figure 45. pixel timing diagram ? 1/4 resolution ? xldr ? constant hccd timing t r 0 v ?4 v 0 v ?4 v +4.2 v ?1.8 v +3 v ?3 v t e t e t e p1xl shdhg shphg shdlg shplg r2xl r2 4 ? t e
kai?04070 www.onsemi.com 45 pixel t iming ? 1/4 resolution ? xldr pixel t iming ? v ariable hccd timing device pin pattern hor izont al cl ocks video vout rxl r p2xl t e figure 46. pixel timing diagram ? 1/4 resolution ? xldr ? variable hccd timing t r p1xl shdhg shphg shdlg shplg r2xl r2 3 ? t e 0 v ?4 v 0 v ?4 v +4.2 v ?1.8 v +3 v ?3 v t e t e
kai?04070 www.onsemi.com 46 vccd clock edge alignment figure 47. vccd clock rise time, fall time and edge alignment v vcr 90% 10% t vf t vr t v t v t vf t vr
kai?04070 www.onsemi.com 47 mechanical information completed assembly figure 48. completed assembly (1 of 2) 1. see ordering information for marking code. 2. no materials to interfere with clearance through guide holes. 3. units: mm. notes: figure 49. completed assembly (2 of 2) 1. optical center of image is nominally at the package center. 2. units: mm. notes:
kai?04070 www.onsemi.com 48 cover glass figure 50. cover glass 1. substrate = schott d263t eco. 2. dust, scratch, inclusion specification: 10 m maximum size in zone a. 3. mar coated both sides. 4. spectral transmission: a. t > 98.0% 420?435 nm b. t > 99.2% 435?630 nm c. t > 98.0% 630?680 nm 5. units: mm. notes:
kai?04070 www.onsemi.com 49 cover glass transmission figure 51. cover glass transmission 0 10 20 30 40 50 60 70 80 90 100 200 300 400 500 600 700 800 900 transmission (%) wavelength (nm)
kai?04070 www.onsemi.com 50 references for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on environmental exposure, please download the using interline ccd image sensors in high intensity lighting conditions application note (and9183/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com . on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 kai?04070/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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